How to design a synchronous counter 4 bit using JK flip flop that can count up even numbers from 0 to 14, and count down odd numbers from 15 to 0 in 1 system - Quora
![digital logic - Design a 3-Bit Up Synchronous Counter Using JK Flip Flop (odd vs even numbers) - Electrical Engineering Stack Exchange digital logic - Design a 3-Bit Up Synchronous Counter Using JK Flip Flop (odd vs even numbers) - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/KunsM.jpg)
digital logic - Design a 3-Bit Up Synchronous Counter Using JK Flip Flop (odd vs even numbers) - Electrical Engineering Stack Exchange
![logisim - 4-Bit ripple down counter using negative edge-triggered J-K flip flops - Electrical Engineering Stack Exchange logisim - 4-Bit ripple down counter using negative edge-triggered J-K flip flops - Electrical Engineering Stack Exchange](https://i.stack.imgur.com/02YCm.png)
logisim - 4-Bit ripple down counter using negative edge-triggered J-K flip flops - Electrical Engineering Stack Exchange
![Design a 4-bit down counter (decrement by 1) and analyze for the same metrics. Assume that no enable signal is used in this case. Assume the same delay characteristic equation and hold Design a 4-bit down counter (decrement by 1) and analyze for the same metrics. Assume that no enable signal is used in this case. Assume the same delay characteristic equation and hold](https://study.com/cimages/multimages/16/counter7410591331235208632.png)