PDF) Multimode scan: Test per clock BIST for IP cores
Steffen Tarnick's research works | Universität Potsdam, Potsdam and other places
PDF) Detection of Delay Faults in Memory Address Decoders
IVML > People > Phivos Mylonas
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Moduli Set Selection and Cost Estimation for RNS-Based FIR Filter and Filter Bank Design
PDF) Symmetry Measure for Memory Test and Its Application in BIST Optimization
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) A Context-Aware Meeting Room: Mobile Interaction and Collaboration Using Android, Java ME and Windows Mobile
NiDS2022 (Novel & Intelligent Digital Systems) - ATHENS
PDF) Pseudorandom, Weighted Random and Pseudoexhaustive Test Patterns Generated in Universal Cellular Automata
PDF) Efficient Test Compaction for Pseudo-Random Testing
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PDF) Detection of Delay Faults in Memory Address Decoders
PDF) Modeling and Simulation of Efficient March Algorithm for Memory Testing
PDF) UHF Receiver Front-End: Implementation and Analog Baseband Design Considerations
PDF) A Closed-Loop Approach for Improving the Wellness of Low-Income Elders at Home Using Game Consoles
PDF) Arbitrary Two-Pattern Delay Testing Using a Low-Overhead Supply Gating Technique
Education and Information Technologies | Home
PDF) On the generation of pseudo-deterministic two-patterns test sequence with LFSRs.
PDF) High-Level Test Synthesis for Delay Fault Testability
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
PDF) Survival analysis for modeling critical events that communities may undergo in dynamic social networks
PDF) A Low-Cost BIST Scheme for Test Vector Embedding in Accumulator-Generated Sequences
